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儲備模組副工程師 (新竹)

at TSMC

GraduateNo visa sponsorshipC/C++/C#

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**Senior Reserve Module Assistant Engineer (Hsinchu)** - Lead development and maintenance of high-reliability reserve modules, with expertise in VHDL, Verilog, and ASIC/FPGA design. Key responsibilities involve collaborative project management, system-level analysis, and hardware/software integration. Seek proven experience (5+ years) in semiconductor industry. Must have proficiency in CAD tools (e.g., Cadence, Synopsys) and experience with Agile methodologies. Fluent in Mandarin required; English proficiency preferred. Highly experienced applicant (5+ years of relevant experience) needed.