ASIC Design Verification Engineer (Santa Clara, CA)

at Qualcomm

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ASIC Design Verification Engineer (Santa Clara, CA)

at Qualcomm

Mid LevelNo visa sponsorshipC/C++/C#

Posted 16 hours ago

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Compensation: Not specified
City: Not specified
Country: United States

**Senior ASIC Design Verification Engineer needed in Santa Clara, CA. Lead complex verification projects (SystemVerilog/UVM), drive testbench creation, and collaborate with cross-functional teams. Requires BS/MS in ECE/CS, 8+ years' experience, proficiency in hardware description languages, simulation tools (ModelSim/Mentor Graphics), and strong understanding of verification methodologies.**

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