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CPU Physical Design Timing Engineer (Austin, TX)

at Qualcomm

Mid LevelNo visa sponsorshipC/C++/C#

Posted 16 hours ago

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Compensation

Not specified

Currency: Not specified

City

Austin

Country

United States

CPU Physical Design Timing Engineer in Austin, TX. Develops and optimizes PDP timing Budget. Key responsibilities: Analysis and CAD tools usage, top-level timing closure, signoff أشد Tiempo, and STA. Skills required: Expertise in CDC, SDC, and clock domain crossing. Proven experience in EDA tools & STA software. Senior-level role demands strong leadership, guidance to junior engineers. TSMC & UMC tech nodes a plus.