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HW SoC/IP modeling and performance/power analyst Senior or Staff Engineer - Qualcomm - Sophia-Antipolis or Guyancourt, France

at Qualcomm

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HW SoC/IP modeling and performance/power analyst Senior or Staff Engineer - Qualcomm - Sophia-Antipolis or Guyancourt, France

at Qualcomm

Tech LeadNo visa sponsorshipC/C++/C#

Posted 17 hours ago

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Compensation
Not specified

Currency: Not specified

City
Not specified
Country
France

**Senior/Staff HW SoC/IP Modeling & Performance/Power Analyst** at Qualcomm, France. Analyze complex SoC/IP models, optimize performance and power consumption. Key responsibilities include architecture exploration, power/performance analysis, clock-domain crossing, and worst-case data path analysis. Requires 10+ years' experience in SoC/IP design, extensive knowledge of CDNS, Verilog/VHDL, and mastery of power/p-performance analysis tools like Intrinsic or PrimeTime. Experience with custom SoC modeling and fairness analysis is a plus. Collaborate cross-functionally to define and implement power-performance optimizations. Seek Senior or Staff Engineer with strong analytical skills and proven ability to innovate and drive technical decisions. Qualified candidate must have a Masters or PhD in Electrical Engineering or Computer Science.

No additional description provided.

HW SoC/IP modeling and performance/power analyst Senior or Staff Engineer - Qualcomm - Sophia-Antipolis or Guyancourt, France

at Qualcomm

Back to all C/C++ jobs
Qualcomm logo
Industry not specified

HW SoC/IP modeling and performance/power analyst Senior or Staff Engineer - Qualcomm - Sophia-Antipolis or Guyancourt, France

at Qualcomm

Tech LeadNo visa sponsorshipC/C++/C#

Posted 17 hours ago

No clicks

Compensation
Not specified

Currency: Not specified

City
Not specified
Country
France

**Senior/Staff HW SoC/IP Modeling & Performance/Power Analyst** at Qualcomm, France. Analyze complex SoC/IP models, optimize performance and power consumption. Key responsibilities include architecture exploration, power/performance analysis, clock-domain crossing, and worst-case data path analysis. Requires 10+ years' experience in SoC/IP design, extensive knowledge of CDNS, Verilog/VHDL, and mastery of power/p-performance analysis tools like Intrinsic or PrimeTime. Experience with custom SoC modeling and fairness analysis is a plus. Collaborate cross-functionally to define and implement power-performance optimizations. Seek Senior or Staff Engineer with strong analytical skills and proven ability to innovate and drive technical decisions. Qualified candidate must have a Masters or PhD in Electrical Engineering or Computer Science.

No additional description provided.

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