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IP Physicial design engineer (Sr. Lead/Staff)

at Qualcomm

Tech LeadNo visa sponsorshipC/C++/C#

Posted 18 hours ago

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Senior IP Physical Design Engineer needed to lead and mentor teams in creating industry-leading ASICs. Optimize PPA (Power, Performance, Area), floorplan layout, and clock tree synthesis using tools like Design Compiler, Innovus, and RedHawk. Minimum 10+ years' experience in ASIC physical design, with 5+ years in senior roles, and expertise in Cadence tools. Proven ability to drive projects from RTL to GDSII.