Industry not specified

Low Power Design/Methodology Engineer

at Qualcomm

Mid LevelNo visa sponsorshipC/C++/C#

Posted 17 hours ago

No clicks

Compensation

Not specified

Currency: Not specified

City

San Diego

Country

United States

**Low Power Design/Methodology Engineer**: Leverage RP (Reuse, Power) methodologies to design power-efficient ASICs/SoCs. Key responsibilities include floorplanning, clock gating, power optimization, and designing test structures. Required skills: DVFS, power gating, low power design techniques, logic design, Verilog/VHDL, and familiarity with Cadence or Synopsys tools. Ideal candidate has 5+ years of experience, BSEE/MSEE with a focus on VLSI.