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LPASS Design Verification Sr Lead Engineer

at Qualcomm

Tech LeadNo visa sponsorshipC/C++/C#

Posted 16 hours ago

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Compensation

Not specified

Currency: Not specified

City

San Diego

Country

United States

The **LPASS Design Verification Senior Lead Engineer** directs design and verification activities for LPASS (Logic Performance Array Signal Synthesis) ICs. This role requires **high-level @ chips, system-on-chip, digital design, verification**, and proficiency in **verification languages (e.g., SystemVerilog, UVM)**. The engineer will **mentor teams, define test strategies, and improve verification process**. A minimum of **12 years in digital design/verification**, with **5+ years in a leadership capacity**, is required. Familiarity with **vossim, 3D hashing, and blockchain technologies** is a plus.