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MSIP PLL Design Verification Engineer, Sr Lead
at Qualcomm
Tech LeadNo visa sponsorshipC/C++/C#
Posted 18 hours ago
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**Senior MSIP PLL Design Verification Engineer Lead** sought for unique role. Key responsibilities: Develop verification plans, create testbenches, and utilize UVM, SystemC, and Python. Leverage Verilog and VHDL knowledge for PLL design validation. Requires 7+ years' experience in semiconductor verification, with 3+ in PLL. Demonstrated leadership and mentoring abilities crucial. Experience with Cadence tools preferred.
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