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Power Management Systems Design and Verification Engineer

at Qualcomm

Mid LevelNo visa sponsorshipC/C++/C#

Posted a day ago

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**Power Management Systems Design and Verification Engineer**: Design and validate power management ICs (PMICs) for high-voltage applications. Key responsibilities include circuit design, simulation, and verification using tools like Cadence Virtuoso, SPICE, and CVS. Candidate should have 5+ years in mixed-signal IC design, proficient in Cadence tools, and experienced with power management architectures. Strong knowledge of IC design flows, transistor-level design, and electrical engineering principles necessary.