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Principal Engineer – RISC-V CPU Sub-System Architecture - Hod Hasharon / Haifa

at Qualcomm

Tech LeadNo visa sponsorshipC/C++/C#

Posted 16 hours ago

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**Principal Engineer - RISC-V CPU Sub-System Architecture** in Hod Hasharon/Haifa. Architect and enhance RISC-V CPU sub-systems, leverage ownership of designs, and collaborate cross-functionally. Mandatory: 10+ years in SoC arena, expert knowledge in RISC-V, experience with VHDL or Verilog, proficiency in system-level design, and strong programming skills (C/C++). Familiarity with formal verification tools, UVM, and computer architecture principles is essential.