Industry not specified

R&D Engineering, Principal Engineer

at Synopsys

Tech LeadNo visa sponsorshipC/C++/C#

Posted 20 hours ago

No clicks

Compensation: Not specified
City: Not specified
Country: United States

**Principal Engineer - R&D Engineer (Sunnyvale, CA)** Lead cross-functional teams in cutting-edge R&D projects. Define technical strategy, mentor staff, and drive product innovation. Required: 10+ years in engineering, expertise in C++, Python, and Git; proficient in hardware design, testing, and troubleshooting. Experience with hardware-software integration and intimate knowledge of cloud services. BS/MS in EE/CS; PhD preferred.

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are passionate about advancing the boundaries of electronic design automation (EDA) and static timing analysis (STA). Combining deep domain knowledge with practical hands-on experience, you thrive in architecting complex systems that impact the global semiconductor industry. You possess a strong sense of ownership, are comfortable navigating ambiguity, and excel at resolving the most challenging technical problems. Your expertise enables you to analyze system-level tradeoffs, balancing accuracy, scalability, and performance for mission-critical sign-off flows. You are a collaborative influencer--valued for your ability to mentor and guide both senior and junior engineers, and for your skill in articulating architectural direction that aligns with business goals and industry trends.

You are recognized for your proficiency in C/C++ and your ability to design and implement scalable, high-performance codebases. You are adept at identifying systemic issues and providing principled solutions, especially when working directly with customers on tapeout-critical challenges. Your communication skills foster trust and inspire technical excellence across distributed teams. You are proactive in defining long-term strategies and have a proven track record of delivering impactful results in complex, fast-paced environments. Above all, you are driven by a desire to shape the future of silicon innovation, ensuring that the PrimeTime platform remains the industry standard for timing sign-off at advanced technology nodes.

What You'll Be Doing:

* Owning and evolving major architectural components of PrimeTime, including timing engines, path search frameworks, constraint modeling, and distributed/parallel analysis flows.

* Defining long-term technical strategy for accuracy, capacity, runtime, and extensibility in static timing analysis, collaborating closely with senior R&D leadership.

* Driving architectural consistency across PrimeTime, Fusion Compiler integration points, and broader sign-off ecosystems.

* Leading the design and implementation of next-generation STA algorithms addressing multi-billion-cell designs, advanced timing effects, and non-linear behaviors.

* Resolving cross-cutting technical issues and making principled tradeoffs between accuracy, performance, memory footprint, and usability at sign-off.

* Acting as the go-to technical authority for customer escalations, sign-off discrepancies, and complex architectural challenges.

* Diagnosing systemic issues involving SDC interpretation, timing convergence, path pessimism/optimism, and tool correlations across flows.

* Mentoring and influencing engineers through technical reviews, discussions, and leadership--raising the technical bar across the organization.

The Impact You Will Have:

* Shape the architectural direction of PrimeTime, ensuring it remains the industry-leading STA solution for advanced silicon designs.

* Define how PrimeTime scales to meet the complexity and reliability demands of next-generation SoCs.

* Reduce customer risk at tapeout by delivering architectural correctness, predictability, and performance.

* Serve as a technical pillar for a tool that is crucial to the success of global silicon innovation.

* Influence the technical roadmap for sign-off methodology, driving improvements across multiple product releases.

* Enhance collaboration across distributed teams, fostering a culture of technical excellence and innovation.

* Directly impact customer satisfaction by resolving tapeout-critical issues and ensuring robust timing sign-off flows.

What You'll Need:

* MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent demonstrated industry expertise.

* 10 years + of experience in EDA, system software, or similarly demanding technical domains.

* Deep hands-on experience with STA or closely related timing/circuit analysis technologies.

* Expert-level proficiency in C/C++ within large, performance-critical codebases.

* Proven track record of architecting complex systems and defining multi-year technical initiatives.

* Strong foundation in algorithms, data structures, and numerical analysis applied at scale.

* Ability to independently define, justify, and drive technical strategy and architectural decisions.

* Preferred: Experience with PrimeTime, distributed computing, parallel STA, memory-scalable design, and advanced-node design challenges.

Who You Are:

* Strategic thinker with a strong sense of ownership and accountability.

* Collaborative influencer, able to mentor and inspire technical teams.

* Excellent communicator, capable of articulating complex technical concepts to diverse audiences.

* Resilient problem solver who thrives on tackling challenging, high-impact issues.

* Adaptable and proactive, comfortable working in fast-paced and evolving environments.

* Detail-oriented yet able to see the bigger picture, balancing short-term needs with long-term vision.

The Team You'll Be A Part Of:

You will join a world-class R&D team dedicated to advancing the PrimeTime platform, collaborating with experts in static timing analysis, algorithm design, and EDA systems. The team is passionate about delivering innovative solutions that define industry standards for timing sign-off. Together, you will tackle complex architectural challenges, drive technical excellence, and shape the future of silicon design by enabling customers to achieve reliable and high-performance tapeouts.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

#TPG

Back to all C/C++ jobs