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R&D Engineering, Sr Staff Engineer - Totem-SC

at Synopsys

Mid LevelNo visa sponsorshipC/C++/C#

Posted 18 hours ago

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Compensation: Not specified
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**Senior R&D Engineer - Totem-SC**: Leads and mentors teams, conducts research, designs, and integrates semiconductor systems. Expertise in Python, C/C++, Verilog,chip design tools (Synopsys, Cadence), and simulation platforms. Requires 12+ years of experience in semiconductor industry.

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years building software that solves real physics problems, not just abstract algorithms. The kind of work where a performance bottleneck in your code means someone downstream misses tapeout, and you have learned to think three steps ahead because of it. You know the difference between code that compiles and code that scales across distributed systems analyzing billion-transistor designs, and you care deeply about that difference.

You are comfortable moving between gate-level circuit behavior and C++ memory optimization without losing sight of what the end user actually needs: accurate power analysis that finishes before the deadline. When you see a bottleneck, you do not just file a ticket, you dig into the profiler, identify the hot path, and fix it. You have worked on codebases large enough that no one person understands the whole thing, and you have learned how to navigate that without creating technical debt for the next engineer.

You ask the right questions when requirements are thin. You push back when a feature request ignores runtime reality. At Synopsys, you will work on tools that define power integrity and reliability signoff for the most advanced semiconductor nodes shipping today.

What You'll Be Doing

Design, develop, and optimize core algorithms for the Totem product line, focusing on power noise integrity, electromigration, thermal analysis, and electrostatic discharge modeling for advanced nodes including 3DIC, FinFET, and GAA architectures

Build and maintain high-performance C++ code that handles parasitic extraction, transistor-level simulation, and gate-level power analysis across distributed processing environments

Diagnose and resolve complex software defects in large-scale commercial codebases, ensuring correctness, scalability, and maintainability under tight delivery schedules

Optimize tool runtime and memory capacity for designs with billions of transistors, using profiling, parallel processing techniques, and algorithmic improvements

Create unit, regression, and system-level tests that validate new features and changes across the full product stack

Collaborate with technical leads, product management, and field engineers to refine solutions based on customer design challenges at 3nm and beyond

Explore and integrate machine learning and AI techniques to improve accuracy, performance, and predictive capabilities in EDA workflows

The Impact You Will Have

Your code will directly enable signoff accuracy for power and reliability analysis on the most complex ICs shipping in smartphones, data centers, and AI accelerators

Performance improvements you deliver will reduce analysis runtime by hours or days, helping customers meet aggressive tapeout schedules

The algorithms you build will help semiconductor companies navigate the physics challenges of sub-3nm nodes, FinFET, GAA, and 3DIC stacking

Your optimization work will expand the capacity of Totem tools, allowing analysis of larger designs without requiring customers to partition or compromise accuracy

Test frameworks you create will catch regressions before they reach customers, protecting product quality and customer trust

Your collaboration with field teams will translate real-world design pain points into software improvements that matter

Machine learning techniques you integrate will position Synopsys tools at the leading edge of AI-driven semiconductor analysis

What You'll Need

Bachelor's degree in Electrical Engineering, Computer Science, or related field with 5+ years of experience, or Master's degree in the same fields

3+ years of professional experience writing production C or C++ code with deep understanding of memory management, performance optimization, and language fundamentals

Working knowledge of Linux operating systems, including development, debugging, and deployment in Linux environments

Strong foundation in data structures, algorithms, and parallel processing techniques applied to large-scale computational problems

Solid understanding of electronic design at gate level or transistor level, including familiarity with circuit behavior, timing, and power concepts

Experience with Python for scripting, automation, or tool integration is a strong plus

Background in parasitic extraction, transistor-level simulation, gate-level power analysis, IC physical design, or machine learning applications in EDA is a differentiator

Who You Are

You can explain a complex performance tradeoff to a technical lead in two sentences without losing the technical nuance, then turn around and document it clearly for the engineer who maintains it next year

You do not wait for perfect specifications to start coding, you clarify what is firm, identify what is flexible, and make progress while keeping stakeholders aligned

When a customer-reported bug lands in your queue with incomplete reproduction steps, you treat it like a puzzle worth solving, not an annoyance, and you work backward until you find the root cause

You know when to optimize and when to ship, and you can articulate why a 10% runtime improvement matters more in one context than another

You are comfortable reviewing someone else's code and offering constructive feedback that makes the codebase better without making the author defensive

You stay current on advances in semiconductor technology and EDA techniques because you are genuinely curious about how the industry is evolving, not because it is required

The Team You'll Be Part Of

You will join the R&D team responsible for the Totem product line, which delivers signoff-accurate power noise integrity and reliability analysis for advanced semiconductor nodes. This team works on some of the hardest computational and physics problems in EDA, building tools that handle 3DIC, FinFET, GAA, and stacked-die architectures for customers pushing the limits of Moore's Law. The team is global, collaborative, and deeply technical, with engineers who have spent years in this problem space and care about getting the physics right.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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