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RTL Design - Staff engineer

at Qualcomm

Tech LeadNo visa sponsorshipC/C++/C#

Posted 17 hours ago

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**Staff RTL Design Engineer**: Lead team designing high-speed ASICs, optimizing power & performance. Needed: 8+ years of RTL experience, proficiency in Verilog, mastery of HIVEC, timing analysis, and knowledge of bus protocols. Experience with Synopsys, Cadence, or other EDA tools required. bakground in mobile/connectivity ICs a plus. Collaborate cross-functionally in Agile methodology.