Senior Staff R&D Design Technology Integration Engineer (WLP, Bump, Die Sort)
at Qualcomm
Posted 14 hours ago
No clicks
- Compensation
- Not specified
- City
- Country
- Not specified
Currency: Not specified
**Senior Staff R&D Engineer** for Design Technology Integration, focusing on Wafer Level Packaging (WLP), Bump, and Die Sort. Become a crucial part of our R&D team, driving innovation in semiconductor packaging technology. Key responsibilities include developing and integrating advanced design technologies, leading cross-functional projects, and collaborating with external partners. eligibility includes a PhD or Master's in Electrical Engineering, Materials Science, or a related field, with 7+ years of proven experience in semiconductor packaging, particularly in WLP, and strong expertise in materials characterization, process engineering, and statistical data analysis tools. Proficient in CAD tools (e.g., Cadence, Mentor Graphics), FEA software (e.g., ANSYS, COMSOL), and programming languages (Python, Java). Demonstrate a proven track record of published research, patents, or innovative process developments.
No additional description provided.
