SerDes Analog Design Engineer, Sr Staff
at Synopsys
Posted 18 hours ago
No clicks
- Compensation
- Not specified
- City
- Country
- South Korea
Currency: Not specified
**Senior Staff SerDes Analog Design Engineer in Seongnam-si, South Korea** Join Synopsys, pioneers in chip design, verification, and IP integration, driving innovations that shape our world. We seek a **Senior Staff Analog Circuit Design Engineer** with a proven track record in analog and mixed-signal design, particularly in SerDes architectures. Core responsibilities include: - Designing, analyzing, and optimizing CMOS analog and mixed-signal circuits - Collaborating with digital RTL engineers to integrate and validate SerDes IP - Minimizing parasitics and improving circuit performance, targeting stringent power, area, and performance metrics - Conducting simulations, presenting data, and leading peer/customer reviews Ideal candidates boast a proven history (10+ years) in analog/mixed-signal design, specializing in SerDes, with a strong foundation in CMOS fundamentals. Fluent in various design tools (CADENCE, ADS, MATLAB), you've led high-performing teams and thrive in collaborative environments. Your experience in delivering cutting-edge solutions positions you to excel in this role and contribute to our Era of Pervasive Intelligence.
We're looking for Analog Circuit Design Engineer to join our team!
You Are:
You are a highly motivated Analog Circuit Design Engineer with a passion for creating ground-breaking technology. You possess an in-depth understanding of analog and mixed-signal building blocks, especially in the context of SerDes designs. Your expertise in CMOS design fundamentals is complemented by your practical experience in optimizing circuit layouts to minimize parasitics and improve performance. You thrive in collaborative environments, working closely with digital RTL engineers to ensure the highest quality designs. Your strong analytical skills allow you to identify and refine circuit implementations to meet stringent power, area, and performance targets. You are comfortable presenting your simulation data for peer and customer review and take ownership of your designs from concept through to electrical characterization.
What You’ll Be Doing:
- Ensuring analog sub-block performance adheres to SerDes standards and architecture document specifications.
- Identifying and refining circuit implementations to achieve optimal power, area, and performance targets.
- Proposing design and verification strategies that efficiently use simulator features to ensure the highest quality design.
- Overseeing physical layout to minimize the effect of parasitics, device stress, and process variation.
- Partnering with digital RTL engineers on the verification of calibration, adaptation, and control algorithms for analog circuits.
- Presenting simulation data for peer and customer review.
- Taking ownership of analog and mixed-signal building blocks that are integrated as part of a larger SerDes design.
- Documenting design features and test plans.
- Consulting on the electrical characterization of your circuit within the SerDes IP product.
The Impact You Will Have:
- Driving innovation in high-speed analog design, pushing the boundaries of SerDes technology.
- Contributing to the development of silicon-proven IP solutions that reduce integration risk and accelerate time-to-market.
- Enhancing the performance and reliability of Synopsys' IP portfolio, ensuring it meets the highest industry standards.
- Collaborating with cross-functional teams to deliver robust and efficient designs.
- Improving design methodologies and verification strategies to streamline development processes.
- Providing expert insights that influence the future direction of analog circuit design at Synopsys.
What You’ll Need:
- Ph.D. with 5+ years, or MSc with 10+ years of SerDes/High-Speed analog design experience.
- Familiarity with the transistor-level circuit design of fundamental analog and mixed-signal building blocks.
- Silicon-proven experience implementing circuits for analog and mixed-signal building blocks.
- Design experience with some of the following SerDes sub-circuits: receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC.
- Experience optimizing CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
- Awareness of ESD issues (i.e. circuit techniques, layout) and design for reliability (i.e. electro-migration, IR, aging, etc.).
- Experience with EDA tools for schematic entry, physical layout, and design verification.
- Knowledge of SPICE simulators and simulation methods.
- Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
- Experience with TCL, Perl, C, Python, MATLAB.
Who You Are:
- Collaborative and open-minded, thriving in a team-oriented environment.
- Detail-oriented with strong analytical and problem-solving skills.
- Proactive and self-motivated with a strong sense of ownership and accountability.
- Excellent communication skills, capable of presenting complex technical information clearly.
- Flexible and adaptable, able to manage multiple priorities and deadlines.
- Passionate about continuous learning and staying updated with industry trends.
The Team You’ll Be A Part Of:
You’ll join the Solutions Group, which provides high-quality, silicon-proven semiconductor IP solutions for SoC designs. Our portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. You’ll work closely with a diverse team of experts who bring architecture design expertise, pre-verified and customizable IP subsystems, hardening, signal/power integrity analysis, and IP prototyping kits to accelerate IP integration, software development, and silicon bring-up.
SerDes Analog Design Engineer, Sr Staff
at Synopsys
SerDes Analog Design Engineer, Sr Staff
at Synopsys
Posted 18 hours ago
No clicks
- Compensation
- Not specified
- City
- Country
- South Korea
Currency: Not specified
**Senior Staff SerDes Analog Design Engineer in Seongnam-si, South Korea** Join Synopsys, pioneers in chip design, verification, and IP integration, driving innovations that shape our world. We seek a **Senior Staff Analog Circuit Design Engineer** with a proven track record in analog and mixed-signal design, particularly in SerDes architectures. Core responsibilities include: - Designing, analyzing, and optimizing CMOS analog and mixed-signal circuits - Collaborating with digital RTL engineers to integrate and validate SerDes IP - Minimizing parasitics and improving circuit performance, targeting stringent power, area, and performance metrics - Conducting simulations, presenting data, and leading peer/customer reviews Ideal candidates boast a proven history (10+ years) in analog/mixed-signal design, specializing in SerDes, with a strong foundation in CMOS fundamentals. Fluent in various design tools (CADENCE, ADS, MATLAB), you've led high-performing teams and thrive in collaborative environments. Your experience in delivering cutting-edge solutions positions you to excel in this role and contribute to our Era of Pervasive Intelligence.
We're looking for Analog Circuit Design Engineer to join our team!
You Are:
You are a highly motivated Analog Circuit Design Engineer with a passion for creating ground-breaking technology. You possess an in-depth understanding of analog and mixed-signal building blocks, especially in the context of SerDes designs. Your expertise in CMOS design fundamentals is complemented by your practical experience in optimizing circuit layouts to minimize parasitics and improve performance. You thrive in collaborative environments, working closely with digital RTL engineers to ensure the highest quality designs. Your strong analytical skills allow you to identify and refine circuit implementations to meet stringent power, area, and performance targets. You are comfortable presenting your simulation data for peer and customer review and take ownership of your designs from concept through to electrical characterization.
What You’ll Be Doing:
- Ensuring analog sub-block performance adheres to SerDes standards and architecture document specifications.
- Identifying and refining circuit implementations to achieve optimal power, area, and performance targets.
- Proposing design and verification strategies that efficiently use simulator features to ensure the highest quality design.
- Overseeing physical layout to minimize the effect of parasitics, device stress, and process variation.
- Partnering with digital RTL engineers on the verification of calibration, adaptation, and control algorithms for analog circuits.
- Presenting simulation data for peer and customer review.
- Taking ownership of analog and mixed-signal building blocks that are integrated as part of a larger SerDes design.
- Documenting design features and test plans.
- Consulting on the electrical characterization of your circuit within the SerDes IP product.
The Impact You Will Have:
- Driving innovation in high-speed analog design, pushing the boundaries of SerDes technology.
- Contributing to the development of silicon-proven IP solutions that reduce integration risk and accelerate time-to-market.
- Enhancing the performance and reliability of Synopsys' IP portfolio, ensuring it meets the highest industry standards.
- Collaborating with cross-functional teams to deliver robust and efficient designs.
- Improving design methodologies and verification strategies to streamline development processes.
- Providing expert insights that influence the future direction of analog circuit design at Synopsys.
What You’ll Need:
- Ph.D. with 5+ years, or MSc with 10+ years of SerDes/High-Speed analog design experience.
- Familiarity with the transistor-level circuit design of fundamental analog and mixed-signal building blocks.
- Silicon-proven experience implementing circuits for analog and mixed-signal building blocks.
- Design experience with some of the following SerDes sub-circuits: receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC.
- Experience optimizing CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
- Awareness of ESD issues (i.e. circuit techniques, layout) and design for reliability (i.e. electro-migration, IR, aging, etc.).
- Experience with EDA tools for schematic entry, physical layout, and design verification.
- Knowledge of SPICE simulators and simulation methods.
- Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
- Experience with TCL, Perl, C, Python, MATLAB.
Who You Are:
- Collaborative and open-minded, thriving in a team-oriented environment.
- Detail-oriented with strong analytical and problem-solving skills.
- Proactive and self-motivated with a strong sense of ownership and accountability.
- Excellent communication skills, capable of presenting complex technical information clearly.
- Flexible and adaptable, able to manage multiple priorities and deadlines.
- Passionate about continuous learning and staying updated with industry trends.
The Team You’ll Be A Part Of:
You’ll join the Solutions Group, which provides high-quality, silicon-proven semiconductor IP solutions for SoC designs. Our portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. You’ll work closely with a diverse team of experts who bring architecture design expertise, pre-verified and customizable IP subsystems, hardening, signal/power integrity analysis, and IP prototyping kits to accelerate IP integration, software development, and silicon bring-up.
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