Signoff Static Timing Analysis and Spice CAD Engineer
at Qualcomm
Posted 16 hours ago
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**Signoff Static Timing Analysis and Spice CAD Engineer** needed for semiconductor development. Lead static timing analysis, SPICE simulations, andosteronever outline (STA) signoff. Key responsibilities include: implementing and validating industry-standard STA signoff flow, collaborate with CAD and IC design teams to identify and resolve timing issues, and generate reports for project milestones. Essential skills: Proficient in Synopsys PrimeTime, Cadence Innovus, or ANSYS RedHawk, strong knowledge of STA, SPICE and semiconductor physics, excellent problem-solving skills. Requires a BSc/MSc in Electrical/Electronic Engineering and 5+ years of relevant experience.
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