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SOC Design Verification Engineer– Pre-Si/Post-Si Verification

at Qualcomm

Mid LevelNo visa sponsorshipC/C++/C#

Posted 19 hours ago

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Compensation

Not specified

Currency: Not specified

City

San Diego

Country

United States

**SOC Design Verification Engineer** sought for pre-silicon and post-silicon verification. Key responsibilities involve creating and maintaining UVM testbenches, developing verification plans, and driving verification closure for complex SOC designs. Must have 5+ years of experience in SOC verification, expertise in UVM, SystemVerilog, Verilion, and proficient in EDA tools (e.g., Questa, VCS). Experience with Mentor, Synopsys, Cadence tools, and familiarity with Python, TCL a plus. Bachelor's degree in EE/CS; masters preferred.