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STA Design Engineer - Static Timing Analysis - Cork, Ireland

at Qualcomm

Mid LevelNo visa sponsorshipC/C++/C#

Posted 14 hours ago

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Ireland

Design STA Engineer, Cork: Lead static timing analysis (STA) for complex ASICs, ensure design meets performance. Key: STA, Timing Closure, STA tools (e.g., Synopsys PrimeTime, Cadence Tempus), RTL coding, script development, Cadence Innovus, Jazz, 5+ yrs in STA, strong ASIC knowledge, aware of design for testability, M145, SDC, timing exception handling, collaborative teamwork.