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Standard Cell Layout Engineer

at Qualcomm

Mid LevelNo visa sponsorshipC/C++/C#

Posted 18 hours ago

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Compensation

Not specified

Currency: Not specified

City

San Diego

Country

United States

**Standard Cell Layout Engineer:** Design and optimize standard cell libraries for advanced-node semiconductor technology (7nm/5nm/3nm). Key responsibilities: logic design, cell design, timing closure, and library characterization using tools such as Synopsys Custom Compiler, Calibre, and InLay. Requires 3+ years of experience in standard cell layout, strong knowledge of FinFET/ Gate-All-Around (GAA) devices, and familiarity with design rules and technology apps.