(Structural ATPG) APAC Digital SOC Test Engineer
at Qualcomm
Posted 14 hours ago
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**Structural ATPG APAC Digital SOC Test Engineer** sought for innovative semiconductor company. Design and implement test benches for complex digital System-on-Chip (SOC) designs, using VHSIC Hardware Description Language (VHDL). Key responsibilities include ATPG (Automatic Test Pattern Generation) for scan-based testing, and collaboration with multi-disciplinary teams. Required: 5+ years in digital test engineer roles, proven ATPG skills, and experience withyield management tools like Calibre xRC. Proficiency in VHDL, Verilog, and logic design tools like Cadence Genus, is essential. Experience working in APAC timezone and a Bachelor's in EE/MSEE is preferred. Join renowned organization driving next-gen semiconductor advancements.
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