Analog Design, Sr.Staff Engineer-15024
at Synopsys
Posted 4 hours ago
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- Not specified
- City
- Country
- United States
Currency: Not specified
**Senior Staff Engineer - Analog Design (Boxborough, MA)** - Lead and contribute to the design, development, and refinement of high-speed (Multi-Gbps) NRZ & PAM4 SERDES IP at Synopsys. Collaborate with a dynamic R&D team to develop and improve analog integrated circuits in advanced FinFET process nodes. Leverage extensive experience (10+ years) in analog/mixed-signal design, SERDES, and understanding of SerDes standards. Utilize skills in circuit architecture, design strategy, and project leadership. Requires expertise in Cadence Virtuoso, Spectre, HSPICE, and hands-on experience in FinFET and other advanced process nodes. Join us to drive innovations shaping the Era of Pervasive Intelligence.
We Are:
- Ownership of Analog Macro level design
- Tracking and reviewing the work of sub-block owners
- Review SerDes standards and architecture documents to develop analog specifications
- Identify and refine circuit implementations to achieve optimal power, area and performance targets.
- Propose design and verification strategies that efficiently use simulator features to ensure highest quality design.
- Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
- Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits.
- Present simulation data for peer and customer review.
- Mentor and review the progress of junior engineers.
- Document design features and test plans.
- Consult on the electrical characterization of your circuit within the SerDes IP product.
- Advanced degree with 6+ years of SerDes/High-Speed analog design experience.
- In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals.
- Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes
- Experience in leading a small team of designers collaborating on building blocks of a Macro level design
- Detailed design experience with several of the following SerDes sub-circuits:
receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC - Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
- Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.).
- Experience with EDA tools for schematic entry, physical layout, and design verification.
- Knowledge of SPICE simulators and simulation methods.
- Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
- Experience with TCL, Perl, C, Python, MATLAB.
- Innovative, analytical, and detail-oriented problem solver.
- Effective communicator with strong presentation and documentation skills.
- Collaborative team player who thrives in multidisciplinary environments.
- Motivated mentor and coach for junior engineers.
- Adaptable to changing project requirements and new technologies.
- Self-driven and committed to continuous professional development.
#LI-NK4
Analog Design, Sr.Staff Engineer-15024
at Synopsys
Analog Design, Sr.Staff Engineer-15024
at Synopsys
Posted 4 hours ago
No clicks
- Compensation
- Not specified
- City
- Country
- United States
Currency: Not specified
**Senior Staff Engineer - Analog Design (Boxborough, MA)** - Lead and contribute to the design, development, and refinement of high-speed (Multi-Gbps) NRZ & PAM4 SERDES IP at Synopsys. Collaborate with a dynamic R&D team to develop and improve analog integrated circuits in advanced FinFET process nodes. Leverage extensive experience (10+ years) in analog/mixed-signal design, SERDES, and understanding of SerDes standards. Utilize skills in circuit architecture, design strategy, and project leadership. Requires expertise in Cadence Virtuoso, Spectre, HSPICE, and hands-on experience in FinFET and other advanced process nodes. Join us to drive innovations shaping the Era of Pervasive Intelligence.
We Are:
- Ownership of Analog Macro level design
- Tracking and reviewing the work of sub-block owners
- Review SerDes standards and architecture documents to develop analog specifications
- Identify and refine circuit implementations to achieve optimal power, area and performance targets.
- Propose design and verification strategies that efficiently use simulator features to ensure highest quality design.
- Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
- Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits.
- Present simulation data for peer and customer review.
- Mentor and review the progress of junior engineers.
- Document design features and test plans.
- Consult on the electrical characterization of your circuit within the SerDes IP product.
- Advanced degree with 6+ years of SerDes/High-Speed analog design experience.
- In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals.
- Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes
- Experience in leading a small team of designers collaborating on building blocks of a Macro level design
- Detailed design experience with several of the following SerDes sub-circuits:
receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC - Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
- Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.).
- Experience with EDA tools for schematic entry, physical layout, and design verification.
- Knowledge of SPICE simulators and simulation methods.
- Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
- Experience with TCL, Perl, C, Python, MATLAB.
- Innovative, analytical, and detail-oriented problem solver.
- Effective communicator with strong presentation and documentation skills.
- Collaborative team player who thrives in multidisciplinary environments.
- Motivated mentor and coach for junior engineers.
- Adaptable to changing project requirements and new technologies.
- Self-driven and committed to continuous professional development.
#LI-NK4
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