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ASIC Digital Design, Manager

at Synopsys

Tech LeadNo visa sponsorshipOther

Posted 18 hours ago

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Compensation: Not specified
City: Noida
Country: India

**ASIC Digital Design Manager** leads LPDDR PHY IP team, driving innovation in high-performance, low-power solutions. Manage digital design and mixed-signal teams, mentoring and guiding engineers. Key responsibilities include: - Define and implement digital design strategies for next-gen LPDDR PHY IP products. - Collaborate with analog designers and lietistics for seamless product integration. - Deliver projects on schedule, meeting quality and performance targets. Requires **12+ years** in ASIC digital design, with **5+ years** in management. Proven expertise in LPDDR PHY, DVFS, DLLs, and clocking. Experience with **Synopsys tools** like Design Compiler, PrimeTime, and VCS essential. Familiarity with **Verilog, SystemVerilog**, and **Python** preferred. Bachelor's or Master's degree in Electrical or Computer Engineering.

Synopsys is at the heart of all the advanced silicon design, we supply the essential tools and intellectual properties to enable semiconductor design, verification, and production. We’re powering all state-of-the-art design market with the world’s most advanced technologies for chip design and software security.

LPDDR PHY IP is a staple of the mixed-signal IP market, and Synopsys is the leading provider of LPDDR PHY IP products. All current and next-generation technologies are being developed by the LPDDR PHY IP team, both digital and analog components, complement each other in creating a high-performance, high-bandwidth, low-latency and low-power products.

We are looking for an ASIC Digital Design Sr. Manager to join Synopsys LPDDR PHY IP team to lead innovation and development of the world-class market-leading DesignWare LPDDR PHY IP solution.

Job Description

Be part of a global diverse team that pushes boundaries on DDR PHY IP development and solution
Your passion and expertise will shape the next generation of product innovation, performance, and efficiency
You will manage a team of design engineers and work with Architect, Verification, Physical implementation, and Firmware teams
In this role, you will contribute to all phases of designs of DDR PHY IP from design specification to productization, including certain level of customer support into their SoCs
You will lead the team to deliver the design and achieve the best timing, performance, and power goals

Required Skills

BS in Electrical Engineering with at least 12-15 years of experience in complex technical development
2 years of experience in people management, developing employees
Experience with synthesizable Verilog and System Verilog design concepts and implementation
Experience with front-end design flows including linting, synthesis, STA, cross-domain clocking, DFT, and power optimization techniques
Exhibit excellent communication skills and be self-motivated
Understanding of memory and memory PHY architecture is a plus

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