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CPU Server Physical Design Clock Engineer

at Qualcomm

Mid LevelNo visa sponsorshipOther

Posted 4 hours ago

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Compensation

Not specified

Currency: Not specified

City

San Diego

Country

United States

**CPU Server Physical Design Clock Engineer**: Designs, optimizes, and validates analog and digital clocking circuits for high-speed, low-power CPUs. Needs 8+ years' experience in clock distribution network design. Proficiency in timing analysis tools (e.g., Synopsys PrimeTime, ANSYS RedHawk) and physical design flows (e.g., Cadence Innovus, Synopsys IC Compiler) crucial. Must have strong understanding of SRAM, logic, and clock tree synthesis. Familiarity with digital design flows and low-power techniques a plus. Collaborates with cross-functional teams to meet power, performance, and area targets.