Annapurna Labs, an Amazon company, designs and delivers high-performance custom silicon at the heart of AWS. Our chips don't just support the cloud — they define it. From Trainium, the purpose-built ML accelerator driving the next wave of AI innovation, to Graviton, the Arm-based processor redefining price-performance for compute workloads, to Nitro, the advanced network and cloud management controller that underpins every AWS instance — Annapurna's products set the standard for the industry.

Founded by industry veterans and operating as a fabless semiconductor company within AWS, Annapurna Labs combines the agility of a startup with the scale of the world's largest cloud provider. Our engineers work with cutting-edge technologies to innovate and shape the future of cloud computing — designing the leading-edge semiconductor products that power Amazon's infrastructure. Here, you'll experience a fast-paced environment with continuous learning opportunities and the chance to develop next-generation platforms.

Join Annapurna Labs and take part in developing cutting-edge semiconductor products within a disruptive system architecture that fuels AWS Nitro- the technology behind millions of servers worldwide.

Watch these videos to learn more about Annapurna Labs:
AWS re:Invent 2025 - Keynote with Peter DeSantis and Dave Brown: https://www.youtube.com/watch?v=JeUpUK0nhC0
AWS re:Invent 2025 - Deep Dive into the AWS Nitro System https://www.youtube.com/watch?v=cD1mNQ9YbeA
AWS re:Invent 2025 - AWS Graviton https://www.youtube.com/watch?v=haSHl2BLhm8
Reducing design for test (DFT) effort with Tessent Streaming Scan Network (SSN) - Dan Trock, Amazon https://www.youtube.com/watch?v=CYpqna1ac-4

Key job responsibilities
As a DFT Engineer at Annapurna Labs (AWS), you'll take ownership of testability architectures and DFT logic, driving their development and verification through the full hardware lifecycle. Your responsibilities may include:

• Define and implement DFT architectures for complex SoC designs
• Develop and integrate DFT logic including: MBIST (Memory Built-In Self-Test), JTAG/TAP, and boundary scan
• RTL coding and debug of DFT controllers and infrastructure using Verilog/SystemVerilog
• Drive gate-level simulations to validate DFT functionality and test patterns
• Develop and verify DFT logic using UVM-based testbenches, functional simulation, and coverage-driven verification
• Participate in design reviews, DFT sign-off processes, and tapeout preparation
• Cross-functional collaboration with Design, Verification, Physical Design, and Production/Test teams


About the team
We are a passionate group of engineers dedicated to creating revolutionary semiconductor solutions. Our team thrives on innovation, collaboration, and continuous learning. We believe in empowering each team member to contribute unique perspectives and drive technological advancement.

Basic Qualifications

- Hands-on experience in RTL design using Verilog/System Verilog
- Experience with chip design flows and gate-level simulations

Preferred Qualifications

- Experience with DFT design and implementation (MBIST, JTAG/IEEE 1149.1, memory repair flows) and familiarity with industry-standard EDA tools such as Synopsys DFT Compiler and Tessent
- Verification background including UVM testbenches, coverage-driven verification, FPGA, and emulator environments, with advanced scripting skills in Perl, Tcl, and/or Python
- End-to-end chip development experience- from RTL design through synthesis, timing analysis, and physical design constraints to post-silicon validation, production, and memory fault debugging

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