
Electro-Magnetic Design Engineer, Senior
at Qualcomm
Posted 2 minutes ago
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- Compensation
- Not specified
- City
- Country
- India
Currency: Not specified
**Senior Electro-Magnetic Design Engineer** at Qualcomm India. Lead RF passive component design for 5G/6G and future gen RFICs in 28nm/14nm/6nm/2nm CMOS/SOI tech. Key responsibilities: **EM simulation, circuit modeling, component optimization**. Essential **RFIC, EM, PCB layout**, **PA/LNA matching** experience. Assets: **PDN, RF transmission line, patch antenna** knowledge. Collaborate with circuits team, drive **next-gen RF components**.
Company:
Qualcomm India Private LimitedJob Area:
Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:
- Design and develop RF passive components for use in the next generation of highly integrated RF integrated circuits in deep sub-micron 28nm/14nm/6nm/2nm CMOS and SOI technologies.
- Work with the circuit design team to optimize component sizes and performance for use in on-chip RF circuit blocks.
- Deliver components that include compact models, and DRC clean physical designs.
- Execute isolation analysis and optimization to reduce on-chip and chip to package coupling.
- Optimization of multichip carriers for RF systems, focusing on loss and isolation.
- Participate in RF package, module, and PCB modeling to optimize overall system performance
- Experience in the design and simulation of RF passive components such as inductors, transformers, MOM/MIM capacitors and passive filters.
- Demonstrated abilities with EM simulation techniques and tool including MoM EM solvers and HFSS.
- Experience with circuit design and layout using Cadence tools and Agilent ADS.
- Compact RLCK Model extraction of multiport passive components.
- Ability to use EM tools to predict circuit level electric and magnetic coupling.
- Understanding of Chip fabrication process and design understanding
- Electromagnetic theory, microwave theory and design
- Antenna design and understanding of radiation and propagation wave
- Good understanding of SI and PI at chip, package, and PCB level
- Basic RF system understanding
- Understanding of noise propagation mechanism in chip, package, and PCB
- Tools: Ansys Suit (HFSS, Q3D, SiWave, Layout), Lorentz, Helic, EMX, Cadence virtuoso, Allegro or similar for Package/Module layout, Expedition (or similar) for PCB layout and schematic, VRF
- Passionate self-starter and team player with experience in project leadership and multi-tasking.
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
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