Infra Design Verification Sr Lead Engineer
at Qualcomm
Posted 21 hours ago
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- Compensation
- Not specified
- City
- Country
- India
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**Infra Design Verification Sr Lead Engineer | Qualcomm India** - Lead team in designing & verifying DDR Subsystem for Infrastructure IP. - Develop & maintain testbenches, verification plans, and methodologies for complex digital systems. - Leverage expertise in C, SystemVerilog, UVM, and bus functional models. - Requires 10+ years' experience in verification, with a track record in DDR interfaces. - Collaborate cross-functionally to ensure product success. - BS/MS in CE/EE/CS or related field.
Company:
Qualcomm India Private LimitedJob Area:
Engineering Group, Engineering Group > Hardware EngineeringGeneral Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Job Overview
We are looking to hire a strong DV engineer to work on verification of DDR Subsystem in the Infra IP team
Create DV infrastructure for verification
Integrate VIP's
Create and execute test plans, debug failures, write assertions, close code and functional coverage
Ensure high quality verification
Working with all stakeholders to ensure program success
Minimum Qualifications
Bachelor's degree in Engineering, Electronics, Information Systems, Computer Science, or related field.
5+ years Hardware Engineering experience or related work experience.
Preferred Qualifications
Following skill set is required:
Strong Debug, UVM, System Verilog
Understanding Specs and Standards and developing relevant test plans
Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved
Candidates should be comfortable checking our builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug, Must be willing to dig into fail and understand what is happening
Preferred Qualifications 5+ Year of industry experiences in the following areas: -
Thorough understanding of Digital design concepts
Thorough understanding dv methodologies and tools
Good understanding of LPDDR4/LPDDR5 protocols
Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite
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