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LPDDR IP Design Principle Engineer

at Synopsys

Tech LeadNo visa sponsorshipOther

Posted 5 hours ago

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Compensation: Not specified
City: Bengaluru
Country: India

**LPDDR IP Design Principal Engineer** in Bengaluru, India. Lead LPDDR PHY IP development, balancing high performance, low power, and low latency. Key responsibilities: architecture design, digital/analog synthesis, and complex I/O interface management. Required skills: strong experience in LPDDR PHY IP design, expertise in Cadence and Synopsys tools, proficiency in Verilog, and knowledge of LPDDR standards. Senior-level role within DesignWare LPDDR PHY IP team.

Synopsys is at the heart of all the advanced silicon design, we supply the essential tools and intellectual properties to enable the semiconductor design, verification, and production. We’re powering all state-of-the-art design market with the world’s most advanced technologies for chip design and software security.

LPDDR PHY IP is a staple of the mixed-signal IP market, and Synopsys is the leading provider of LPDDR PHY IP products. All current and next-generation technologies are being developed by the LPDDR PHY IP team, both digital and analog components, complement each other in creating a high-performance, high-bandwidth, low-latency and low-power products.

We are looking for Sr. Staff ASIC Digital Design Engineer to join Synopsys LPDDR PHY IP team to innovate and develop the latest world-class market-leading DesignWare LPDDR PHY IP solution. Be part of a global diverse team that pushes boundaries on LPDDR PHY IP development and solution, your passion and expertise will shape the next generation of product innovation, performance, and efficiency.

Job Description

In this role, you will be in a leadership role to contribute to all phases of designs of DDR PHY IP from design specification to productization, including certain level of customer support into their SoCs.

Designing and micro-architecting LPDDR PHY IP writing Verilog and SystemVerilog code and design specification

Conduct simulation and analysis of designs working with Verification, Timing, DFT, and Power team members

Analyzing and fixing Lint, CDC/RDC, DFT, Timing, and power issues

Maintain and improve design automating flow and process

Required Skills

BS in Electrical Engineering and a minimum of 10 years of experience in complex technical development

Experience with synthesizable Verilog and System Verilog design concepts, coding, and implementation

Experience with front-end design flows such as linting, synthesis, timing investigation and closure, cross-domain clocking, DFT, and power optimization techniques

Exhibit excellent communication skills and be self-motivated

Understanding of memory and memory PHY architecture is a plus

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