
Package Manufacturing Engineer, Senior to Staff Level (Kaohsiung or Taichung)
at Qualcomm
Posted 9 hours ago
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**Senior-Level Package Manufacturing Engineer - Kaohsiung/Taichung** Lead cross-functional matrix teams, driving product development for Qualcomm's diverse ecosystem, including bumping, WLP, Flip Chip CSP, BGA, SiP, EMIB, CoWoS, CPO, and 2.5/3D Chiplet applications. Manage technical risks, material/design selections, and develop processes from concept to production. Oversee substrate and assembly processes, SPC, control plans, FMEAs, and risps. Collaborate with Design, Device process development, and internal/external packaging groups. Requires 10+ years of semiconductor packaging experience.
Company:
Qualcomm Semiconductor LimitedJob Area:
Engineering Group, Engineering Group > Hardware EngineeringGeneral Summary:
Overview
Exhibit skill and confidence in working cross-functionally across a matrix organization in a very dynamic and fast-paced environment
Support development of products and advanced technologies for Qualcomm bumping, WLP, Flip Chip CSP& BGA , SiP module, EMIB, CoWoS, CPO, Data center, ASIC, SIP, Server, Rack, and 2.5/3D Chiplet applications
Support product material and design selections, technical risk assessments, mitigation plans, and development from concept to production
Candidate will develop a strong understanding of substrate and assembly process details, SPC, Control plans, OCAPs, FMEAs, PCN, CARs
Candidate will work cross-functionally with Design, Device process development, internal and subcontract Packaging groups
Minimum Qualifications
10+ years of relevant work experience in Semiconductor (Packaging) Engineering or Manufacturing
Deep understanding of packaging requirements, process capability and equipment capability throughout the industry and the ability to incorporate best engineering practices for all backend assembly process included automotive products requirements
Familiar with excel, JMP data analysis tool
Basic knowledge of excel VBA, Tableau software
Good understanding of Chip level and package level reliability and failure analysis methodology
Understand yield management, continuous improvement, assembly cycle time analysis and cost reduction
Fluent in English and Mandarin, both spoken and written
Proactive working attitude and capable to handle new challenge
Preferred Qualifications
Good knowledge of quality concept and RMA process
Basic knowledge of foundry process
Good understanding of wafer bumping, laser grooving, wafer saw, Pick and place, underfill and Heat spread processes
Good experience with yield management software (O+), JMP analysis tool
Understand assembly and test house working model, turnkey model, supply chain and KPI
Education Requirements
Preferred Master's degree in Electrical Engineering, Physics, Materials Science, or related discipline; Good Bachelor candidate with wide spectrum may be considered as well.
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
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