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Principal (STA/ Sign-Off) Engineer-17042 (Austin/ Sunnyvale)

at Synopsys

Tech LeadNo visa sponsorshipOther

Posted 17 hours ago

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Compensation: Not specified
City: Austin
Country: United States

**Principal Sign-Off Engineer (STA) - 17042 (Austin/Sunnyvale)** Lead ASIC design methodology, defining best-in-class standards and flows. Collaborate globally with IP development teams to drive next-gen SerDes, memory interfaces, and subsystems. Key responsibilities include: defining and adhering to sign-off rules, guiding teams through physical design, and ensuring design closure. Proficient in STA (Static Timing Analysis) tools, knowledge of Cadence Innovus/Genus/Tempus, and asynchronous clocking experience crucial. Minimum 8+ years in digital ASIC design, with 3+ in senior or lead roles. This Principal Engineer-1 role offers opportunities in Austin or Sunnyvale, calf.

The Hiring Manager is open to hiring in 'Austin' and 'Sunnyvale' both for this position.

As a member of the IP Digital Design Methodology team, you will work with global teams to define best in class ASIC design standards and flows and assist IP development teams. You will be involved with next generation SerDes and Memory interface controllers, PHYs, and subsystems.

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced ASIC Digital Signoff Engineer with a deep passion for developing cutting-edge technology and direct hands-on experience with STA and EM/IR flows. With over 12+ years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development. You have a solid understanding of digital design flows and deep expertise in Static Timing Analysis (STA), Power Analysis, and EM/IR for advanced node designs. Your technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams. Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results. You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.

What You’ll Be Doing:

Develop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries.
Work with leading edge designs and teams to drive the industry-best PPA for IP designs.
Evaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO’s.
Develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials.
Work as a liaison between Synopsys tool and IP design teams.
Continuously improve and refine design processes to enhance efficiency and performance.

What You’ll Need:

BS or MS in EE with 12+ years of hands-on experience developing CAD flows for high-speed digital IP cores and/or SOCs.
Direct hands-on experience with enabling advanced node STA/ Timing signoff flows at SoC level.
Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.
Familiarity with EMIR & Thermal sign-off flows is a plus.
Ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results.
Good analysis, debugging, and problem-solving skills.
Solid written and verbal communication skills and the ability to create clear and concise documentation and provide training.
Familiarity with other Synopsys tools such as StarRC and ICV is a plus.
Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR are a plus.

The Impact You Will Have:

Drive innovation in high-speed digital IP core and Subsystem development.
Enhance the efficiency and effectiveness of our design and verification processes.
Contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems.
Ensure the highest quality standards in the design and implementation of our products.
Facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence.
Support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.

Who You Are:

You are a collaborative and innovative engineer with a strong technical background and a passion for excellence. You thrive in a dynamic environment and enjoy working with global teams to achieve common goals. Your ability to communicate effectively and your commitment to continuous improvement make you an invaluable asset to our team.

The Team You’ll Be A Part Of:

You will join the Interface IP Digital Design Methodology team, working with global teams to define best practice ASIC design standards and flows. This team is dedicated to supporting IP development teams and is involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.

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