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Processor Micro Architect RTL Design Engineer (Multiple Levels)

at Qualcomm

Back to all Other jobs
Qualcomm logo
Industry not specified

Processor Micro Architect RTL Design Engineer (Multiple Levels)

at Qualcomm

Mid LevelNo visa sponsorshipOther

Posted 3 hours ago

No clicks

Compensation
Not specified

Currency: Not specified

City
San Diego
Country
United States

**Processor Microarchitecture RTL Design Engineer** sought for multiple levels. **Design** power-efficient **microarchitectures** for **high-performance CPUs**. **Key responsibilities** include **RTL** coding, **verification**, and **simulation**. **Required skills**: C, Verilog, VHDL, **functional verification**, **timing analysis** ( Synopsys, PrimeTime). **Experience levels**: Senior (8+ yrs), Staff (5-8 yrs), andentry-level (fresh college graduates or 0-2 yrs). Collaborate cross-functionally, **troubleshoot** hardware/software **issues**, and **optimize** performance. **Proficient in**icier, RV64, RV32, and RISC-V **ISA**.

No additional description provided.

Processor Micro Architect RTL Design Engineer (Multiple Levels)

at Qualcomm

Back to all Other jobs
Qualcomm logo
Industry not specified

Processor Micro Architect RTL Design Engineer (Multiple Levels)

at Qualcomm

Mid LevelNo visa sponsorshipOther

Posted 3 hours ago

No clicks

Compensation
Not specified

Currency: Not specified

City
San Diego
Country
United States

**Processor Microarchitecture RTL Design Engineer** sought for multiple levels. **Design** power-efficient **microarchitectures** for **high-performance CPUs**. **Key responsibilities** include **RTL** coding, **verification**, and **simulation**. **Required skills**: C, Verilog, VHDL, **functional verification**, **timing analysis** ( Synopsys, PrimeTime). **Experience levels**: Senior (8+ yrs), Staff (5-8 yrs), andentry-level (fresh college graduates or 0-2 yrs). Collaborate cross-functionally, **troubleshoot** hardware/software **issues**, and **optimize** performance. **Proficient in**icier, RV64, RV32, and RISC-V **ISA**.

No additional description provided.

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