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R&D Advanced Packaging Integration Engineer
at TSMC
Mid LevelNo visa sponsorshipOther
Posted 9 hours ago
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**R&D Advanced Packaging Integration Engineer:** Engineer excels in integrated circuit (IC) packaging, leading cross-functional teams to develop and optimize complex packaging solutions. Must have 7+ years of experience in semiconductor packaging, expertise in flip chip, wafer-level packaging, and 3D integration. Proficiency in hands-on lab experiments and statistical analysis. Familiarity with Cadence Virtuoso, Mentor Graphics tools and ASITIC/TSV technology essential. Bachelor's degree required, Master's degree preferred.
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