
RTL Design (NOC/Interconnect) -Staff
at Qualcomm
Posted 16 hours ago
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"Staff RTL Design Engineer needed for NOC/Interconnect roles. Design and verify complex Verilog RTL, in collaboration with multi-site teams. Leverage Mathworks MATLAB & Simulink for simulation, VCS/NCSim for simulation & assertions, Cadence Incisive for synthesis, and Synopsys PrimeTime/ RAF for timing analysis. Requires a BS/MS degree in ECE/CS, 6-8+ years' RTLdesign experience, expertise in UVM verification, and proficient use of versioning systems (e.g., Git).
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