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RTL Design(Turing) - Sr Engineer
at Qualcomm
Mid LevelNo visa sponsorshipOther
Posted 17 hours ago
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**RTL Design Senior Engineer.** Leads RTL design for complex SoCs, utilizing VHDL/Verilog. Requires 7+ years' experience, with 3+ in senior roles. Must be proficient in UVM/SV, SystemVerilog, and low-power design techniques. Proven expertise in Cadence, Synopsys tools. Expects onshore experience, with remote collaboration.
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