Senior SOC Physical Design Engineer
at Qualcomm
Posted 7 hours ago
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- Compensation
- $146,717 – $190,100 USD
- City
- Country
- Not specified
Currency: $ (USD)
**Senior SOC Physical Design Engineer** with Qualcomm: Lead SoC physical design for high-speed DDR & graphics. Key responsibilities include floor planning, clock tree synthesis, place & route, PDN, timing analysis & closure. Perform physical verification checks. Collaborate cross-functionally to meet tapeout signoff. Requires Master's in EE, CE, or CS.
Company:
Qualcomm Technologies, Inc.Job Area:
Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:
This individual independently plans, performs the moderately-defined responsibility for the Physical Design Flow of high-speed DDR, graphics, physical verification flows, microarchitecture, SOC algorithm design and modeling, and methodology, focusing on target power utilization and optimization for system-on-chip (SoC) products and how these features impact power and performance. Responsibilities include: Floor Planning, Clock Tree Synthesis, Place and Route, PDN, Timing analysis and closure. Performs various physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield) at the chip and block levels. Provides schedules and support cross-functional engineering effort to drive to signoff closure for tapeout. Acts as a strong contributor at design reviews and project meetings.
Will accept a Master's Degree (or foreign academic equivalent) in Electrical Engineering, Computer Engineering, Computer Science or related degree field.
Pay Range: $146,717.00 - $190,100.00/year
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