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Senior Staff RTL Design Engineer- 16908

at Synopsys

Tech LeadNo visa sponsorshipOther

Posted 17 hours ago

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Compensation: Not specified
City: Not specified
Country: United States

**Senior Staff RTL Design Engineer** in Boxborough, MA (16908). Lead complex RTL development, delivering production code for advanced semiconductor IP. Leverage expertise in timing closure, power optimization, and design quality. Requires 10+ years' experience in ASIC digital design, Utilize expertise with Synopsys tools (HC08, VCS, PrimeTime) and SystemVerilog/Verilog HDL. Proven track record of driving complex projects to success.

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You bring extensive ASIC digital design experience with a track record of delivering production RTL for complex semiconductor IP. Your expertise encompasses timing closure, power optimization, and design quality across advanced process nodes.

You work effectively across organizational boundaries, collaborating with architecture, analog, verification, and physical design teams. You manage technical tradeoffs systematically, balancing performance, area, and power requirements while maintaining schedule commitments. When faced with evolving specifications, you provide data-driven analysis and practical solutions. At Synopsys, you will contribute to LPDDR PHY IP that powers mobile and AI applications in production silicon worldwide.

What You'll Be Doing

Design RTL modules for LPDDR PHY IP from microarchitecture through synthesis-ready implementation
Optimize designs to meet timing, power, and area targets across multiple process nodes
Develop Perl automation for design generation and flow integration
Collaborate with cross-functional teams to resolve timing and power challenges
Contribute to design reviews and methodology development

The Impact You Will Have

Your designs will enable LPDDR PHY IP deployed in high-volume mobile, automotive, and AI products
You will contribute to a major revenue-generating product line for Synopsys
Your work will define performance characteristics for customer systems-on-chip
Your automation will improve design efficiency across the engineering team
Your expertise will influence architectural decisions for future products

What You'll Need

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
10+ years of ASIC digital design experience with RTL ownership in production silicon
Expert Verilog proficiency for timing-critical designs
Strong Perl scripting skills for design automation
Deep knowledge of synthesis, timing analysis, and power optimization
Experience with PHY IP or high-speed interfaces is preferred

Who You Are

You understand how RTL structure affects timing and power outcomes
You communicate effectively across technical disciplines
You produce maintainable code that supports collaboration
You identify process improvements proactively
You resolve technical issues through systematic analysis

The Team You'll Be Part Of

You will join the team responsible for microarchitecture and front-end design of LPDDR PHY IP. This core product generates significant revenue and enables critical functionality in customer designs across mobile, automotive, and AI markets.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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