Senior Staff_Ethernet Switch ASIC Design
at Qualcomm
Posted 3 minutes ago
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- Compensation
- Not specified
- City
- Country
- China
Currency: Not specified
**Senior Staff Ethernet Switch ASIC Design Engineer at Qualcomm China:** Leverage deep expertise in ASIC development and Ethernet switch architecture to drive next-gen switch/ PON ASICs. Key responsibilities include: defining architecture and roadmap for Ethernet switching and packet processing; leading multi-subsystem designs. Required: proven ASIC development experience (logic design, RTL coding, verification, synthesis, timing closure, physical design); solid leadership and problem-solving skills; proficiency in Chinese and English.
Company:
Qualcomm China
Job Area:
Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:
Requirements:
- Deep expertise in ASIC development, especially logic design, RTL coding, verification, synthesis, timing closure and physical design flow
- Deep expertise in Ethernet switch architecture, including:
- Forwarding pipelines (L2/L3, ACLs, tunneling)
- Traffic management (QoS, scheduling, shaping)
- High-performance packet processing and scaling strategies
- Strong leadership and cross-functional influence capability
- Strong debugging and system-level problem-solving skills
- Excellent teamwork, interpersonal and communication skills.
- Fluent in Chinese and English both verbal and written.
- Ability to work in stressful situations with tight schedules to meet.
Description of Function & Responsibility
- Drive architecture definition and technical strategy for next-generation Ethernet switch or PON ASICs, enabling scalable, high-performance networking solutions.
- Define architecture and roadmap for Ethernet switching and packet processing subsystems
- Lead design across multiple subsystems (forwarding engine, traffic management, scheduling, resource allocation)
- Drive cross-functional alignment with HW, SW, and Product teams on networking features and performance targets
- Lead performance analysis, modeling, and trade-off studies for switch architecture
- Mentor senior technical leaders and influence organization-wide engineering direction
- Ensure successful execution from architecture through silicon delivery
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
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