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SOC Engineering, Sr Staff Engineer- RTL Design

at Synopsys

Tech LeadNo visa sponsorshipOther

Posted 18 hours ago

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Compensation: Not specified
City: Noida
Country: India

**SOC Engineering, Sr Staff Engineer - RTL Design** in Noida, India. Design RTL for complex SoCs, mentor junior engineers. Required: 10+yrs exp in RTL design, proficiency in Verilog/SystemVerilog, expertise in low-power design techniques. Familiarity with UVM, SV-Lib, Cadence Genus/Innovus a plus. Experience with chip bring-up and debug.

Job Title:

SoC RTL Design Engineer, Sr Staff

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years building and signing off RTL that actually ships in silicon, not just passes simulation. The difference between a design that tapes out clean and one that comes back with a respin is usually a clock domain crossing someone missed or a constraint someone wrote too loosely, and you are the engineer who catches those things before they become problems. You know that static checks are not checkbox exercises, they are conversations with the design, and you have learned to read what Spyglass is actually telling you beneath the noise.

You have debugged enough CDC violations to know which ones matter and which ones are artifacts of tool setup. You have written enough SDC to know when a constraint is fighting the architecture instead of describing it. Running synthesis is not a handoff for you, it is part of how you validate that your RTL decisions were sound. You do not need someone to tell you what good looks like, you have a point of view on design quality and you are comfortable defending it in a review.

Working across IP integration, subsystem assembly, and full SoC builds does not intimidate you. You have done it before, and you know how to move between abstraction levels without losing sight of what actually has to work in the end.

What You'll Be Doing

Run RTL quality signoff using Spyglass for LINT, CDC, and RDC checks across IP blocks, subsystems, and full SoC designs

Develop timing constraints in SDC for synthesis and static timing analysis, ensuring constraints accurately reflect design intent and architecture

Execute preliminary synthesis runs using Design Compiler or Fusion Compiler to validate RTL synthesizability, area, and timing feasibility before handoff

Perform formal equivalence checking with Formality to verify RTL-to-gate consistency across design revisions and ECOs

Integrate third-party and Synopsys IP into customer SoCs and subsystems, resolving integration issues related to clocking, reset, and interface protocols

Create and modify RTL design blocks to meet customer-specific requirements, working within established design guidelines and delivery timelines

Collaborate with verification, implementation, and architecture teams to close signoff issues and ensure RTL quality gates are met before tapeout

The Impact You Will Have

Your signoff rigor directly reduces respin risk for customers building chips in advanced nodes where a single CDC bug can cost months and millions

The constraints you write become the foundation for physical implementation teams to close timing, making or breaking their ability to meet PPA targets

Your synthesis validation catches architectural mismatches early, preventing costly surprises downstream in place and route

The IP integrations you deliver enable startups and tier-one customers to meet aggressive tapeout schedules with confidence in design quality

Your expertise in static verification tools shapes internal methodology, raising the bar for what clean RTL means across the System Solutions Group

The RTL you design and integrate becomes part of production SoCs powering AI, automotive, 5G, and IoT applications in the field

Your work helps Synopsys customers tape out some of the most complex and challenging semiconductor designs in the industry

What You'll Need

Bachelor's or Master's in Electronics Engineering, Electrical Engineering, or Computer Engineering with 8+ years of hands-on experience in RTL design and verification

Proven experience performing static verification using Spyglass or equivalent tools for LINT, CDC, and RDC analysis on complex digital designs

Strong working knowledge of synthesis tools such as Design Compiler or Fusion Compiler, including constraint development and synthesis quality checks

Hands-on experience with Formality or equivalent formal verification tools for RTL-to-gate equivalence checking

Solid conceptual understanding of clock domain crossing, reset domain crossing, and common design pitfalls that lead to metastability or functional failures

Experience integrating IP blocks into subsystems or SoCs, including resolving interface, clocking, and protocol issues

Familiarity with scripting in Tcl, Python, or Perl to automate checks, reporting, and design flows is a strong plus

Who You Are

You can look at a CDC report with 500 violations and know within an hour which ten actually need fixing and which are tool noise or acceptable design choices

You write constraints that implementation teams can actually use, not overly conservative SDC that makes timing impossible or loose constraints that let real problems slip through

You push back when an architecture decision is going to create a signoff nightmare three months later, and you do it with enough specificity that people listen

You are comfortable working with customers directly, translating their requirements into RTL decisions without needing everything spelled out in a specification

You stay current on what good RTL practice looks like as nodes shrink and design complexity grows, and you bring that knowledge into reviews and mentoring

You can context-switch between a 10-gate glue logic fix and a multi-thousand-line subsystem integration without losing attention to detail on either

The Team You'll Be Part Of

You will join the System Solutions Group, a team of specialists in Synopsys technologies who deliver architecture, design, verification, implementation, tools, and methodology to help customers complete their most challenging SoC projects. The work spans from sub-blocks to full turnkey SoCs, and customers range from startups to industry leaders across commercial and government sectors. This is a global team working on real production designs that tape out and ship in silicon.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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