SoC Physical Design Engineer, Sr Staff
at Synopsys
Posted 17 hours ago
No clicks
- Compensation
- Not specified
- City
- Country
- Not specified
Currency: Not specified
**Senior Staff SoC Physical Design Engineer in Taipei** Lead SoC physical design projects, utilizing expertise in top-down design, floor planning, clock and STA. Leverage tools like Cadence Innovus, ICC2, and Synopsys IC Compiler. Manage junior engineers. Requires 10+ years' experience, proven track record in SoC physical design, and familiarity with advanced nodes (7nm and below). Must have excellent communication skills and ability to thrive in collaborative, dynamic teams. Proficient in Cadence/Synopsys flow and proficient English skills required.
- Collaborating with other FE and BE engineers or customer engineers to assist in successful tape-outs from RTL to GDS or from Netlist to GDS using Synopsys EDA tools
- Focusing on areas such as physical implementation, IR/EM, physcial verification and timing closure.
- Working as a member of the customer's IC design team, providing immediate impact on their current project while transferring valuable knowledge for future projects
- Interacting regularly with customers to identify and eliminate barriers to project success
- Planning and managing the delivery of your own project-related tasks
- Leveraging the entire Synopsys team to ensure project success and providing feedback to R&D/AE on suggested tool enhancements or issues
- Working with or as a Project Leader to develop technical proposals, working through the project life cycle, and producing consistently high-quality technical solutions.
- Enhancing the efficiency and success of customer tape-outs
- Providing expert knowledge and best practices to customer IC design teams
- Identifying and eliminating barriers to project success, ensuring timely delivery
- Contributing to the continuous improvement of Synopsys EDA tools through feedback
- Developing high-quality technical solutions that meet customer needs
- Strengthening Synopsys' reputation as a leader in chip design and verification
- Facilitating knowledge transfer for future customer projects.
- 10+ years of industry experience in SOC engineering
- Expertise in physical implementation and timing closure
- Experience with STA and IR/EM
- Knowledge of UPF and low power techniques (preferred)
- Strong verbal and written English communication skills
- Excellent customer interfacing abilities
- A collaborative team player with a proactive approach
- A sophisticated professional with advanced knowledge and wide-ranging experience
- An effective communicator capable of interacting with diverse stakeholders
- Highly organized and able to manage complex issues with minimal supervision
- A problem solver with a keen eye for detail and quality
SoC Physical Design Engineer, Sr Staff
at Synopsys
SoC Physical Design Engineer, Sr Staff
at Synopsys
Posted 17 hours ago
No clicks
- Compensation
- Not specified
- City
- Country
- Not specified
Currency: Not specified
**Senior Staff SoC Physical Design Engineer in Taipei** Lead SoC physical design projects, utilizing expertise in top-down design, floor planning, clock and STA. Leverage tools like Cadence Innovus, ICC2, and Synopsys IC Compiler. Manage junior engineers. Requires 10+ years' experience, proven track record in SoC physical design, and familiarity with advanced nodes (7nm and below). Must have excellent communication skills and ability to thrive in collaborative, dynamic teams. Proficient in Cadence/Synopsys flow and proficient English skills required.
- Collaborating with other FE and BE engineers or customer engineers to assist in successful tape-outs from RTL to GDS or from Netlist to GDS using Synopsys EDA tools
- Focusing on areas such as physical implementation, IR/EM, physcial verification and timing closure.
- Working as a member of the customer's IC design team, providing immediate impact on their current project while transferring valuable knowledge for future projects
- Interacting regularly with customers to identify and eliminate barriers to project success
- Planning and managing the delivery of your own project-related tasks
- Leveraging the entire Synopsys team to ensure project success and providing feedback to R&D/AE on suggested tool enhancements or issues
- Working with or as a Project Leader to develop technical proposals, working through the project life cycle, and producing consistently high-quality technical solutions.
- Enhancing the efficiency and success of customer tape-outs
- Providing expert knowledge and best practices to customer IC design teams
- Identifying and eliminating barriers to project success, ensuring timely delivery
- Contributing to the continuous improvement of Synopsys EDA tools through feedback
- Developing high-quality technical solutions that meet customer needs
- Strengthening Synopsys' reputation as a leader in chip design and verification
- Facilitating knowledge transfer for future customer projects.
- 10+ years of industry experience in SOC engineering
- Expertise in physical implementation and timing closure
- Experience with STA and IR/EM
- Knowledge of UPF and low power techniques (preferred)
- Strong verbal and written English communication skills
- Excellent customer interfacing abilities
- A collaborative team player with a proactive approach
- A sophisticated professional with advanced knowledge and wide-ranging experience
- An effective communicator capable of interacting with diverse stakeholders
- Highly organized and able to manage complex issues with minimal supervision
- A problem solver with a keen eye for detail and quality
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