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Application Engineering, Staff Engineer - Physical Verification (Runset Development)

at Synopsys

Mid LevelNo visa sponsorshipPython

Posted 18 hours ago

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Compensation: Not specified
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**Staff Engineer - Physical Verification (Runset Development)**: Lead team in designing and optimizing physical verification runsets. **Key Responsibilities**: Develop and maintain runsets for advanced node physical verification flows, troubleshoot and optimize layout vs. schematic (LVS) and design rule checks (DRC). **Required Skills**: Proficient in Millennium, Calibre, and Mentor Graphics tools. Minimum 7 years in semiconductor physical verification, expert understanding of design rule alignment. **Location**: Hsinchu, Taiwan.

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology. With 5-8 years of industry experience—primarily in Physical Verification (PV)—you thrive on solving complex layout and verification challenges for advanced process nodes. You possess a deep understanding of transistor CMOS layouts, ASIC design flows, and have hands-on expertise with industry-standard EDA tools such as IC Validator, Calibre, and Pegasus. Your proficiency in scripting languages like Perl, Tcl, and Python enables you to automate and optimize PV runset development, ensuring high-quality deliverables.

You are committed to continuous learning and improvement, keeping pace with evolving foundry processes and design for manufacturability (DFM) requirements. As a natural collaborator and mentor, you enjoy guiding junior team members and fostering a supportive team environment. Your excellent communication skills empower you to engage confidently with customers and field application engineers (FAEs), translating complex requirements into innovative solutions. You are detail-oriented, resourceful, and dedicated to exceeding customer expectations, making you a valuable asset to any high-performing engineering team.

What You’ll Be Doing:

Developing and validating DRC, LVS, and Fill runsets (rule deck files) for the Synopsys IC Validator tool, targeting state-of-the-art semiconductor technologies.

Collaborating closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes.

Automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.

Troubleshooting and resolving complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges.

Interfacing directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions.

Mentoring junior team members, sharing best practices, and contributing to a knowledge-sharing culture within the team.

Staying up-to-date with the latest EDA tool advancements, competitive products, and foundry process innovations to maintain Synopsys’ technical edge.

The Impact You Will Have:

Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses.

Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market.

Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps.

Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges.

Contribute to the development of next-generation verification methodologies and best practices within Synopsys.

Strengthen Synopsys’ reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support.

What You’ll Need:

B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field.

5-8 years of hands-on experience in the Physical Verification (PV) domain.

Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS.

Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development.

Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements.

Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks.

Exposure to competitive EDA tools and awareness of their strengths and limitations.

Who You Are:

An analytical thinker with strong problem-solving abilities and meticulous attention to detail.

A collaborative team player who fosters knowledge sharing and mentorship.

Effective communicator, capable of translating technical concepts to diverse audiences.

Adaptable and proactive, with a passion for continuous learning and innovation.

Customer-focused, with a commitment to delivering high-quality solutions on time.

Self-driven, organized, and able to manage multiple priorities in a fast-paced environment.

The Team You’ll Be A Part Of:

You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You’ll work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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