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Staff Design Engineer, Networking, Google Cloud

at Alphabet

Back to all C/C++ jobs
A
Industry not specified

Staff Design Engineer, Networking, Google Cloud

at Alphabet

Tech LeadNo visa sponsorshipC/C++/C#

Posted 5 hours ago

No clicks

Compensation
Not specified

Currency: Not specified

City
Tel Aviv
Country
Israel

Be part of a team developing Application-specific integrated circuits (ASICs) that accelerate networking in Google's data centers. You will lead an ASIC subsystem, define hardware/software interfaces, and drive micro-architecture and design specifications. Collaborate with software, verification, and physical design teams to ensure complete, correct, and high-performance designs. The role emphasizes ownership of outcomes, solving complex problems, and delivering scalable networking hardware for Google Cloud.

Staff Design Engineer, Networking, Google Cloud

  • Copy link
  • Email a friend
GoogleTel Aviv, Israel; Haifa, Israel
Advanced
  • Copy link
  • Email a friend
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 10 years of experience architecting networking ASICs from specification to production.
  • Experience developing Register-Transfer Level (RTL) for ASIC subsystems.
  • Experience with cross-functional engagement in micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:

  • Experience working with software teams optimizing the hardware/software interface.
  • Experience working with design networking like: Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
  • Experience in Transmission Control Protocol (TCP), IP, Ethernet, Peripheral Component Interconnect Express (PCIE) and Dynamic Random Access Memory (DRAM) including Network on Chip (NoC) principles and protocols (AXI, ACE, and CHI).
  • Experience architecting networking switches, end points, and hardware offloads.
  • Understanding of packet classification, processing, queuing, scheduling, switching, routing, traffic conditioning, and telemetry.
  • Proficiency in procedural programming language (e.g., C++, Python, Go).

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing Application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for a networking stack.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

  • Lead an ASIC subsystem.
  • Understand how ASIC subsystem interacts with software and other ASIC subsystems to implement data center networks.
  • Define hardware/software interfaces. Write micro architecture and design specifications.
  • Define efficient micro-architecture and block partitioning/interfaces and flows.
  • Collaborate with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Staff Design Engineer, Networking, Google Cloud

at Alphabet

Back to all C/C++ jobs
A
Industry not specified

Staff Design Engineer, Networking, Google Cloud

at Alphabet

Tech LeadNo visa sponsorshipC/C++/C#

Posted 5 hours ago

No clicks

Compensation
Not specified

Currency: Not specified

City
Tel Aviv
Country
Israel

Be part of a team developing Application-specific integrated circuits (ASICs) that accelerate networking in Google's data centers. You will lead an ASIC subsystem, define hardware/software interfaces, and drive micro-architecture and design specifications. Collaborate with software, verification, and physical design teams to ensure complete, correct, and high-performance designs. The role emphasizes ownership of outcomes, solving complex problems, and delivering scalable networking hardware for Google Cloud.

Staff Design Engineer, Networking, Google Cloud

  • Copy link
  • Email a friend
GoogleTel Aviv, Israel; Haifa, Israel
Advanced
  • Copy link
  • Email a friend
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 10 years of experience architecting networking ASICs from specification to production.
  • Experience developing Register-Transfer Level (RTL) for ASIC subsystems.
  • Experience with cross-functional engagement in micro-architecture, design, verification, logic synthesis, and timing closure.

Preferred qualifications:

  • Experience working with software teams optimizing the hardware/software interface.
  • Experience working with design networking like: Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
  • Experience in Transmission Control Protocol (TCP), IP, Ethernet, Peripheral Component Interconnect Express (PCIE) and Dynamic Random Access Memory (DRAM) including Network on Chip (NoC) principles and protocols (AXI, ACE, and CHI).
  • Experience architecting networking switches, end points, and hardware offloads.
  • Understanding of packet classification, processing, queuing, scheduling, switching, routing, traffic conditioning, and telemetry.
  • Proficiency in procedural programming language (e.g., C++, Python, Go).

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing Application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for a networking stack.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

  • Lead an ASIC subsystem.
  • Understand how ASIC subsystem interacts with software and other ASIC subsystems to implement data center networks.
  • Define hardware/software interfaces. Write micro architecture and design specifications.
  • Define efficient micro-architecture and block partitioning/interfaces and flows.
  • Collaborate with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

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