ASIC Verification Engineer - PMU
at Nvidia
Posted 8 hours ago
No clicks
- Compensation
- Not specified
- City
- Shanghai
- Country
- China
Currency: Not specified
Join NVIDIA's PMU IP verification team as an ASIC Verification Engineer - PMU. You will define the IP verification methodology with the IP architect, and lead the verification effort for new features across projects. You will maintain and improve the UVM-based unit-level testbench, manage regression suites, and apply formal verification techniques to boost verification quality. The role involves working on the PMU IP (RISC-V core + custom control logic) to optimize power points across idle and active scenarios, requiring solid IC background and strong SystemVerilog/UVM skills.
As chip sizes continue to grow, power efficiency has become critical across all NVIDIA products - from data centers to automotive and personal computing. Our PMU IP, developed over the past 17 years, is crucial in optimizing chip performance and efficiency in both idle and active scenarios. The PMU IP consists of a RISC-V core and custom-designed control logic. It collects and processes data from the entire chip, working in tandem with software running on the RISC-V core to determine optimal operating points. We are seeking a Senior Verification Engineer to join our Power Management Unit (PMU) IP team to help building more powerful PMU engine.
What you’ll be doing:
Co-work with the IP architect and designer to define the IP verification methodology and test plan. Finishing the IP verification for all new coming features from project to project.
Maintain and improve the UVM based unit-level TB to be powerful and efficient. Maintain the regression and run various of sing-off verification checklists.
Learn and practice formal verification, and use formal tool to assist simulation to raise the verification quality.
What we need to see:
BS with 4+ years of experience or MS with 2+ years of working experience.
Self-driving, active thinking and problem solving.
Solid IC background.
Experienced with System Verilog and UVM methodology. Familiar with perl or python script. Familiar with C/C++ coding.
Fluent oral and written English.
Ways to stand out from the crowd:
Have the experience of building a complex TB from scratch.
Good at solving environment issues. Like setting up Makefile, solving VCS issue, or solving issues brought by tool updates, etc.
Good communication skills. State problem clearly.
