Senior CAD Developer - Timing and Physical Design Optimization
at Nvidia
Posted 9 hours ago
No clicks
- Compensation
- Not specified
- City
- Shanghai
- Country
- China
Currency: Not specified
The role covers physical design from RTL to GSDII including design quality checks, synthesis, formal checks, partitioning, constraints, async checks, timing analysis and signoff, along with related flows. You will invent and optimize methods to increase chip frequency while reducing power across internal optimization tools. You will improve C++ algorithms for gate-level sizing, buffering, useful clock skew, cell legalization, and IR drop optimization. You will own the full process from discovery and invention of optimization opportunities to developing solutions and working directly with design teams to deploy them.
ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow. Join us, you will work together with expertise in all these areas; you will not only work for physical application, but also drive physical friendly design with all related teams: ASIC/P&R/DFT/SI/ARCH etc.; you will work for the most advanced process/technology, the biggest chip in the world.
What You’ll Be Doing:
Invent and optimize new methods for increasing chip frequency while minimizing power consumption across a suite of internal optimization tools.
Improve algorithms (in C++) for gate-level sizing, buffering, useful clock skew, cell legalization, IR drop optimization
As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.
What We Need To See:
BS, MS, PhD in Electrical Engineering or Computer Science or equivalent experience
Minimum 5+ years of relevant experience in CAD software and VLSI hardware design
Strength in both CAD software and VLSI design
Understanding of VLSI timing optimization and related concepts, including timing constraints, corners, power, etc.
Demonstrated ability in software development using C++
Familiarity with design implementation tools such as PrimeTime, Tempus, ICC2, Innovus, SeaHawk, and typical design flows written in Perl, Tcl, and Python.
Strong communication and interpersonal skills
Ways To Stand Out From The Crowd:
C++14 or newer experience, such as lambdas and concurrency
Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use, etc.
Experience in IR drop optimization, calculation
