CPU Architecture Performance Engineer, Senior to Staff Level
at Qualcomm
Posted 18 hours ago
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- Compensation
- Not specified USD
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The main responsibility is performance verification for world-class custom CPU for mobile and portable computers. The role requires proficiency in CPU architecture areas such as fetch, decode, branch prediction, renaming, execute units, SIMD, load/store, MMU, caches and retirement. You will verify performance features between RTL and models and troubleshoot issues. You will collaborate with design and performance teams to develop test cases and validate new features.
Company:
Qualcomm Semiconductor LimitedJob Area:
Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:
The Potential Areas To Work Include
The main responsibility of this position is to do the performance verification for world-class custom CPU for mobile and portable computers.
Roles and Responsibilities
Proficiency in one or more areas of CPU architecture: fetch, decode, branch prediction, renaming, execute units, SIMD, load/store, MMU, caches, retire, etc.
Verify performance feature between RTL and model, and have ability to troubleshooting
Work with design team and performance team to develop test case and validate new feature
Preferred qualifications
MS degree in Computer Architecture with 3-5 years of practical experience
Good CPU architecture knowledge and micro-architecture knowledge
Experience working in a RTL simulation environment
Experience working in a performance modeling environment
Proficient in Verilog, C and C++ and scripting languages such as Perl or Python
Ability to problem solve and prove your own ideas
Knowledge and experience with common performance benchmarks and workloads
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
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