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DDR PHY Timing Design Engineer
at Qualcomm
Mid LevelNo visa sponsorshipC/C++/C#
Posted 5 hours ago
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Design and verify DDR PHY timing and signal integrity in memory interfaces, including timing closure, timing budgets, and PVT analysis. Collaborate with chip architects, RTL/physical design teams, and validation to ensure robust DDR PHY performance. Develop and maintain scripts and flows for STA, DRC/DFT checks, and sign-off criteria. Contribute to debug, characterization, and power-performance optimizations for a high-volume mobile/compute SoC.
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