This individual leads, plans, synthesizes ambiguous or conflicting requirements and performs the complex responsibility of the use of tools/applications (i.e., Cadence Virtuoso, Simvision, Verisium, Xcelium, RTL Compiler, MATLAB, etc.) to execute the architecture, design and verification of an individual block according to design protocol provided. Participates in developing an implementation strategy that meets system requirements and customer needs, occasionally relying on help from manager. Resolves architecture, design, or verification problems by applying sound ASIC engineering practices with minimal supervision. Owns the design and verification strategies of ASICs, Soc, and IP cores of a single block or IC Package. Writes tests and regressions to identify any bugs in own work and helps more junior team members do the same. Runs power checks on a single block to ensure it meets specifications provided by team lead. Interprets the results of performance checks and reports them to team lead. Provides ideas and furthers the innovation of ASICs, Soc, IP cores, and/or transistor level integrated circuits verification. Writes, reviews, and edits technical document in accordance with template requirements. Communicates directly with lead on any significant deviations from the Plan of Record for assigned block in a timely manner. Provides input (i.e., timing. feasibility) on assigned tasks related to projects. Provides input on process improvement by identifying existing resources or work products that can be reused or applied to assigned tasks. Acts as a strong contributor at design reviews and project meetings and communicates and implements a development plan.