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RTL Design Engineer, Machine Learning

at Alphabet

Back to all Data Science / AI / ML jobs
A
Industry not specified

RTL Design Engineer, Machine Learning

at Alphabet

Tech LeadNo visa sponsorshipData Science/AI/ML

Posted 2 hours ago

No clicks

Compensation
$156,000 – $229,000 USD

Currency: $ (USD)

City
Not specified
Country
United States

Join Google to shape the future of AI/ML hardware acceleration by driving the design and verification of TPU architecture components. You will develop and verify one or more blocks of a custom ASIC/SoC, collaborating with software, architecture, and cross-functional teams. This role focuses on RTL design using Verilog/SystemVerilog and involves working on high-performance, power-efficient AI hardware powering Google's TPU and ML workloads. The role offers opportunities to mentor others and contribute to cutting-edge hardware infrastructure used by Google Cloud and billions of users.

RTL Design Engineer, Machine Learning

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GoogleSunnyvale, CA, USA
Mid
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  • Email a friend

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 8 years of experience with custom silicon design (SoCs, ASICs, etc.).
  • Experience with RTL (Register Transfer Level) design using Verilog or SystemVerilog.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience interacting with software, architecture, and other cross-functional teams.
  • Experience with a scripting language (e.g., Python or Perl).
  • Experience applying engineering best practices (e.g., code review, testing, refactoring).
  • Knowledge of processor design, accelerators, or memory hierarchies and machine learning algorithms.
  • Knowledge of high performance and low power design techniques.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

  • Understand the overall application of the chip, proposing and developing improvements in overall design.
  • Design and document one or more blocks of an ASIC, including functionality and timing.
  • Work closely with software teams on functionality, interfaces, and documentation.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

RTL Design Engineer, Machine Learning

at Alphabet

Back to all Data Science / AI / ML jobs
A
Industry not specified

RTL Design Engineer, Machine Learning

at Alphabet

Tech LeadNo visa sponsorshipData Science/AI/ML

Posted 2 hours ago

No clicks

Compensation
$156,000 – $229,000 USD

Currency: $ (USD)

City
Not specified
Country
United States

Join Google to shape the future of AI/ML hardware acceleration by driving the design and verification of TPU architecture components. You will develop and verify one or more blocks of a custom ASIC/SoC, collaborating with software, architecture, and cross-functional teams. This role focuses on RTL design using Verilog/SystemVerilog and involves working on high-performance, power-efficient AI hardware powering Google's TPU and ML workloads. The role offers opportunities to mentor others and contribute to cutting-edge hardware infrastructure used by Google Cloud and billions of users.

RTL Design Engineer, Machine Learning

  • Copy link
  • Email a friend
GoogleSunnyvale, CA, USA
Mid
  • Copy link
  • Email a friend

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 8 years of experience with custom silicon design (SoCs, ASICs, etc.).
  • Experience with RTL (Register Transfer Level) design using Verilog or SystemVerilog.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience interacting with software, architecture, and other cross-functional teams.
  • Experience with a scripting language (e.g., Python or Perl).
  • Experience applying engineering best practices (e.g., code review, testing, refactoring).
  • Knowledge of processor design, accelerators, or memory hierarchies and machine learning algorithms.
  • Knowledge of high performance and low power design techniques.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

The US base salary range for this full-time position is $156,000-$229,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

  • Understand the overall application of the chip, proposing and developing improvements in overall design.
  • Design and document one or more blocks of an ASIC, including functionality and timing.
  • Work closely with software teams on functionality, interfaces, and documentation.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

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