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ASIC Intern - 2026

at Nvidia

Back to all Python jobs
N
Industry not specified

ASIC Intern - 2026

at Nvidia

InternshipNo visa sponsorshipPython

Posted 8 hours ago

No clicks

Compensation
Not specified

Currency: Not specified

City
Shanghai
Country
China

NVIDIA MMPLEX team in Shanghai is seeking ASIC Design Interns to work with senior engineers on design methodology and workflow efficiency. You will build AI-assisted automation/tools to accelerate RTL/design/verification, prototype and deploy scripts that integrate with existing toolchains, and collaborate to improve PPA via better flows and quality gates. This role offers learning of world-leading IP development practices and opportunities to modernize engineering workflows. Candidates pursuing a Master's in EE/CS or related field with fundamentals in digital design and Verilog/SystemVerilog, plus basic C/C++ and Python skills, are encouraged to apply.

We are looking for ASIC Design Interns! NVIDIA MMPLEX team is based in Shanghai with more than 300 team members. We deliver cutting-edge IP solutions across NVIDIA product lines including datacenter, GeForce, Automotive, and Networking. Our IPs include micro-processors, security, DL/CV accelerators, display, video encoder/decoder, and image processing.

In this internship, you’ll work closely with senior engineers on design methodology and workflow efficiency, including building AI-assisted automation/agents to improve how we design, verify, and debug hardware IP. Join us if you want to learn world-leading IP development practices and help modernize engineering workflows.

What you’ll be doing:

  • Design methodology development: improve existing RTL/design/verification workflows with automation and best practices

  • Build AI agents/tools to accelerate engineering tasks

  • Collaborate with senior engineers to improve PPA via better flows, debugging efficiency, and quality gates

  • Prototype and deploy scripts/services that integrate with existing toolchains

What we need to see:

  • Pursuing a Master’s degree in EE/CS or related field

  • Solid fundamentals in digital design and Verilog/SystemVerilog

  • Basic C/C++ programming skills

  • Hands-on experience using existing AI/LLM models to accomplish engineering tasks

  • Familiarity with prompting and evaluating model outputs (accuracy, hallucination handling, reproducibility)

  • Fluent English with good communication and documentation skills

Ways to stand out from the crowd:

  • Prior experience building AI agents (tool-using agents, RAG, workflow automation) for technical tasks

  • Experience with prompt engineering, prompt tuning/iteration, and creating reusable prompt templates/playbooks

  • Python proficiency (plus Shell/Makefile/Perl) and comfort integrating with real engineering workflows

  • Familiar with ASIC design/verification process and tools (lint, CDC/RDC, synthesis, simulation/regression)

  • Strong ownership: can take an ambiguous workflow problem and turn it into a measurable efficiency/quality improvement

ASIC Intern - 2026

at Nvidia

Back to all Python jobs
N
Industry not specified

ASIC Intern - 2026

at Nvidia

InternshipNo visa sponsorshipPython

Posted 8 hours ago

No clicks

Compensation
Not specified

Currency: Not specified

City
Shanghai
Country
China

NVIDIA MMPLEX team in Shanghai is seeking ASIC Design Interns to work with senior engineers on design methodology and workflow efficiency. You will build AI-assisted automation/tools to accelerate RTL/design/verification, prototype and deploy scripts that integrate with existing toolchains, and collaborate to improve PPA via better flows and quality gates. This role offers learning of world-leading IP development practices and opportunities to modernize engineering workflows. Candidates pursuing a Master's in EE/CS or related field with fundamentals in digital design and Verilog/SystemVerilog, plus basic C/C++ and Python skills, are encouraged to apply.

We are looking for ASIC Design Interns! NVIDIA MMPLEX team is based in Shanghai with more than 300 team members. We deliver cutting-edge IP solutions across NVIDIA product lines including datacenter, GeForce, Automotive, and Networking. Our IPs include micro-processors, security, DL/CV accelerators, display, video encoder/decoder, and image processing.

In this internship, you’ll work closely with senior engineers on design methodology and workflow efficiency, including building AI-assisted automation/agents to improve how we design, verify, and debug hardware IP. Join us if you want to learn world-leading IP development practices and help modernize engineering workflows.

What you’ll be doing:

  • Design methodology development: improve existing RTL/design/verification workflows with automation and best practices

  • Build AI agents/tools to accelerate engineering tasks

  • Collaborate with senior engineers to improve PPA via better flows, debugging efficiency, and quality gates

  • Prototype and deploy scripts/services that integrate with existing toolchains

What we need to see:

  • Pursuing a Master’s degree in EE/CS or related field

  • Solid fundamentals in digital design and Verilog/SystemVerilog

  • Basic C/C++ programming skills

  • Hands-on experience using existing AI/LLM models to accomplish engineering tasks

  • Familiarity with prompting and evaluating model outputs (accuracy, hallucination handling, reproducibility)

  • Fluent English with good communication and documentation skills

Ways to stand out from the crowd:

  • Prior experience building AI agents (tool-using agents, RAG, workflow automation) for technical tasks

  • Experience with prompt engineering, prompt tuning/iteration, and creating reusable prompt templates/playbooks

  • Python proficiency (plus Shell/Makefile/Perl) and comfort integrating with real engineering workflows

  • Familiar with ASIC design/verification process and tools (lint, CDC/RDC, synthesis, simulation/regression)

  • Strong ownership: can take an ambiguous workflow problem and turn it into a measurable efficiency/quality improvement

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