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Physical Design CAD Engineer

at Nvidia

Back to all Python jobs
N
Industry not specified

Physical Design CAD Engineer

at Nvidia

GraduateNo visa sponsorshipPython

Posted 4 hours ago

No clicks

Compensation
Not specified

Currency: Not specified

City
Not specified
Country
Israel

NVIDIA is seeking a Physical Design CAD Engineer to develop physical design, synthesis, STA and timing closure methodologies for networking chips and SOCs. You will collaborate with block owners and full-chip STA engineers to ensure high-quality, timely convergence, and contribute to flow/tool methodologies for floorplanning, power/clock distribution, P&R, timing, and back-end verification. The role requires hands-on experience in physical design, timing, crosstalk/noise analysis, and ECO implementation, with scripting skills in Python/Perl/Tcl. A BSc/MSc in EE/CE with at least 2 years of relevant experience is preferred.

NVIDIA is looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

  • You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs.

  • Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence.

  • Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.

  • Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.

What we need to see:

  • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

  • At least 2 years of relevant experience

  • Proficiency using Python, Perl, Tcl, Make scripting.

  • Expertise in analysing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.

  • Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required and implementing them through ECOs is required.

  • Knowledge in process variation effect modelling and experience in design convergence taking into account variations.

  • Successful track record of delivering designs to production is necessary.

  • Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.

Ways to stand out from the crowd:

  • Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/Tempus)

  • Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an advantage.

  • Great teammate.

  • Ownership, self-learning skills, and ability to work autonomously.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

#LI-Hybrid

Physical Design CAD Engineer

at Nvidia

Back to all Python jobs
N
Industry not specified

Physical Design CAD Engineer

at Nvidia

GraduateNo visa sponsorshipPython

Posted 4 hours ago

No clicks

Compensation
Not specified

Currency: Not specified

City
Not specified
Country
Israel

NVIDIA is seeking a Physical Design CAD Engineer to develop physical design, synthesis, STA and timing closure methodologies for networking chips and SOCs. You will collaborate with block owners and full-chip STA engineers to ensure high-quality, timely convergence, and contribute to flow/tool methodologies for floorplanning, power/clock distribution, P&R, timing, and back-end verification. The role requires hands-on experience in physical design, timing, crosstalk/noise analysis, and ECO implementation, with scripting skills in Python/Perl/Tcl. A BSc/MSc in EE/CE with at least 2 years of relevant experience is preferred.

NVIDIA is looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

  • You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs.

  • Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence.

  • Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.

  • Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.

What we need to see:

  • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

  • At least 2 years of relevant experience

  • Proficiency using Python, Perl, Tcl, Make scripting.

  • Expertise in analysing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.

  • Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required and implementing them through ECOs is required.

  • Knowledge in process variation effect modelling and experience in design convergence taking into account variations.

  • Successful track record of delivering designs to production is necessary.

  • Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.

Ways to stand out from the crowd:

  • Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/Tempus)

  • Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an advantage.

  • Great teammate.

  • Ownership, self-learning skills, and ability to work autonomously.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry!

#LI-Hybrid

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