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ASIC Timing and Methodology Engineer
at Qualcomm
Mid LevelNo visa sponsorshipPython
Posted 5 hours ago
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ASIC Timing and Methodology Engineer responsible for timing closure, clock-domain analysis, and methodology development for ASIC design flows. Works with EDA tools to optimize timing, power, and area, and collaborates with design and verification teams. Requires strong scripting and digital design fundamentals to improve ASIC performance and reliability.
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