Dtech Timing Methodology Engineer
at Qualcomm
Posted 5 hours ago
No clicks
- Compensation
- Not specified
- City
- Not specified
- Country
- Not specified
Currency: Not specified
Responsible for developing and validating timing methodologies for digital design flows. Work includes creating timing models, closure strategies, and statistical analysis across PVT variations to ensure design meet timing targets. Collaborate with RTL/physical design, EDA tool flows and verification teams to implement efficient timing solutions and optimize performance, area, and power. This role emphasizes automation and data-driven decision making to accelerate design closure.
No additional description provided.

